System on a chip (SoC) integrated circuits include assorted subsystems. For example, a smart phone SoC may integrate a modem, a graphics processor, Bluetooth, WiFi, and other subsystems. Each of these subsystems will typically have different timing requirements with regard to entering sleep mode, active mode, or shutdown as compared to the timing requirements for the SoC processor. Given these different timing requirements, it is conventional to power the subsystems independently from the SoC processor. For example, the subsystems may be organized into a “low-power island” powered by two power rails: an island embedded memory (MX) power rail and an island core logic (CX) power rail. The processor would similarly be powered by a processor CX power rail and a processor MX power rail.
Each MX power rail provides the power supply voltage to the various embedded memories within a corresponding embedded memory power domain. The island MX power rail thus provides power to an island embedded memory power domain within the low-power island. Similarly, the processor MX power rail provides power to a processor embedded memory power domain for the SoC processor. In contrast, each CX power rail provides the power supply voltage to the core logic within a corresponding core logic power domain. The island CX power rail thus provides the power supply voltage to the core logic within an island core logic power domain in the low-power island whereas the processor CX power rail provides the power supply voltage to the core logic for the SoC processor. In general, the voltage levels required by the embedded memory power domains are different from those for the core logic power domains. For example, embedded memories require a higher power supply voltage to retain their stored values in the sleep mode as compared to the reduced power supply voltage for powering the logic gates in a sleep mode. If a common power rail were used for both the embedded memories and the core logic, the core logic would waste power during the sleep mode from, for example, unnecessary leakage current loss due to the elevated power supply voltage that would be required to maintain the stored states in the embedded memories. Having independent memory and core logic power domains thus saves power. However, the power grid formed by the conventional memory and core logic power domains faces several challenges that may be better appreciated through the following discussion of a conventional SoC 100 as shown in FIG. 1.
SoC 100 includes a low-power island 110 that includes corresponding subsystems. For example, low-power island 110 may include a sensor sub-system 114 that includes an island CX power domain 111 powered by an island CX power rail 115. In addition, low-power island 110 includes an MX power domain 112 powered by an island embedded memory (MX) power rail 120. An SoC processor (not illustrated) in the remainder of SoC 100 includes an SoC MX power domain 120 powered by an SoC MX power rail 130. A CX power domain and corresponding CX power rail for the SoC processor is not shown for illustration clarity. A power management integrated circuit (PMIC) 105 powers the various power rails within SoC 100. For example, PMIC 105 includes a dedicated switch-mode power supply (MX SMPS) 135 to provide power to SoC MX power rail 130. But switch-mode power supplies are relatively expensive in terms of die area demands so an island SMPS 140 is shared by both island CX power rail 115 and island MX power rail 120. Since the island MX and CX power supply voltages may be different as discussed above, each power rail 115 and 120 couples to island SMPS 140 through a corresponding island linear drop-out regulator (LDO) 150 and 145, respectively. Since each island power rail 115 and 120 has its own corresponding island LDO, their voltages may be independently controlled despite being commonly powered by island SMPS 140. Low-power island 110 is advantageous in that its island power rails 115 and 120 may be placed into sleep mode while the SoC processor is still in active mode. In this fashion, power is not needlessly wasted with regard to supplying low-power island 110 with active-level power supply voltages simply because the SoC processor is active.
Island CX power rail 115 may be completely collapsed (discharged to ground) in the sleep mode. In contrast, island MX power domain 112 would lose its state if the MX power supply voltage on island MX power rail 120 were collapsed during sleep mode. Thus, the MX power supply voltage is maintained at a retention level during the sleep mode for low-power island 110. The MX power supply voltage carried on island MX power rail 120 must thus transition from the active mode power supply voltage level to the retention power supply voltage level when low-power island 110 transitions into the sleep mode. But note that island CX power rail 115, island MX power rail 120 (as well as SoC MX power rail 130) each requires a decoupling capacitor (C) to provide instantaneous power should the corresponding CX or MX power domain suddenly demand power. The capacitances of these decoupling capacitors is relatively large so that the instantaneous power demands may be met. A relatively large amount of charge must thus be discharged to ground from island MX power rail 120 when low-power island 110 transitions to the sleep mode, which reduces battery life accordingly. In addition, island MX LDO 145 wastes power when converting an active-mode power supply voltage from island SMPS 140 to the retention voltage for island MX power rail 120. Another problem with regard to SoC 100 is that the efficiency of a switch-mode power supply such as SMPS 140 tends to drop dramatically at the reduced current output levels associated with the sleep mode of operation for low-power island 110. The reduced power grid efficiency can be quite dramatic.
Accordingly, there is a need in the art for improved power architectures for integrated circuits including independently-powered subsystems.